In contemporary times, there is a significant increase in using displays to communicate visible signals. For more widespread future use, development of the displays focuses on light weight, thin thickness, low energy consumption, low manufacturing cost, and better display quality.
LTPS technique is a new technique to manufacture TFT substrates. Compared to conventional a-Si techniques, LTPS displays exhibit advantages such as quick response speed, high brightness, high degree of resolution, and lower energy consumption.
N-type LTPS TFT substrates, generally having a self-alignment structure, are configured to have a gate electrode covering an underneath non-doped polysilicon region (i.e., channel region) without an overlapping doped region. However, with such conventional design of LTPS TFT substrate, resistance of the lightly doped region is constant and cannot be adjusted, therefore, under higher voltage of drain electrode, there is serious impact ionization in the region of the drain electrode, resulting in kink effect and having unfavorable influence on long-term stable operation of devices.
Therefore, there is a need to solve the problems encountered in the prior art.